In order to enable fabrication of next generation devices and structures, three dimensional (3D) stacking of semiconductor chips is often utilized to improve performance of the transistors. By arranging transistors in three dimensions instead of conventional two dimensions, multiple transistors may be placed in the integrated circuits (ICs) very close to each other. Three dimensional (3D) stacking of semiconductor chips reduces wire lengths and keeps wiring delay low. In manufacturing 3D stacking of semiconductor chips, specific structures (e.g., stair-like structures) are often utilized to allow multiple interconnection structures to be disposed thereon, forming high-density of vertical transistor devices.
When forming features, such as trenches or vias, in stair-like structures in a film stack disposed on a substrate, an etch process using a photoresist layer as an etching mask is often utilized. The film stack comprises multiple material layers in which the features, such as trenches or vias, are formed with high aspect ratios. Aspect ratios (A/R) are generally defined as the ratio between the depth of the feature and the width of the feature. In the past, a 20:1 A/R was considered a high A/R. However, next generation devices and structures attempt A/Rs of 50:1, 60:1 and higher (e.g., 70:1 or more).
However, the inventors have identified some key challenges for performing 3D NAND Memory Hole RIE processes with greater than 40:1 aspect ratios. For example, the etching mask material entrance is easily clogged when performing the RIE processes longer in an attempt to achieve higher aspect ratios (i.e., when trying to create deeper holes/vias). Some other issues experienced include ARDE (Aspect Ratio Dependent Etching) symptoms and Profile Bowing. Specifically, as the etching gets deeper, the etching rate gets slower. As etching rate slows, the productivity of the tool to produce devices is reduced. Etch rates as low as 130 nm/min have been overserved under existing process techniques are higher A/Rs. Furthermore, irregular profiles and growth of the etching by-products may be formed during etching may gradually block the small openings used to fabricate the small critical dimension structures, thereby resulting in bowed, distorted, toppled, or twisted profiles of the etched structures. Redeposition material or build-up of etching by-products may be randomly and/or irregularly adhere to the top surface and/or sidewalls of the film stack, the resulting irregular profile and growth of the redeposition material or etching by-products may alter the flow path of the reactive etchants, resulting in a bowing or twisting profile of the features formed in the film stack.
Thus, there is a need for improved methods for forming high aspect ratio features with accurate profiles and dimension control for three dimensional (3D) stacking of semiconductor chips.